Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even 5 nm, has good properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) ~45 mV/V, and switching (ION/IOFF) ~106 shows a higher level electrostatic integrity. At LG optimized spacer dielectric exhibits ~5 orders improvement in IOFF is less than ~2 20 LG. Thus, from result analysis, dielectrics essential lower for better performance. For continued scaling, HfO2 ensures high lowest downfall ION 11.24% decline 15.8% 13.26% no Si3N4 respectively. With SiO2, Si3N4, spacers an which permissible ITRS low power requirements. Moreover, to flexibility towards analog/RF applications parameters transconductance (gm), generation factor (TGF), total capacitance (Cgg), cutoff frequency (fT) also determined. Furthermore, impact on dynamic (DP) static (SP) consumption presented. The findings show that JL NW one potential candidates future technology nodes.